Method of eliminating back-end rerouting in ball grid array packaging

ABSTRACT

Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

FIELD OF THE INVENTION

[0001] This invention relates to improvements in micro-BGA chip scalepackaging.

BACKGROUND OF THE INVENTION

[0002] Chip scale packaging (CSP) of integrated circuits is a widelyaccepted electronic systems packaging technology. Ball grid array (BGA)packaging, such as the μBGA® package developed by Tessera Technologiesof San Jose, Calif., is often looked to as the chip scale packaging(CSP) method of choice, it being valued for accommodating the mismatchin coefficients of thermal expansion (CTE) between silicon and commonlyused substrates, such as FR-4 epoxy circuit boards.

[0003] The fundamentals of micro-BGA technology are generally summarizedin the six patents set forth below, the disclosures of which areincorporated by reference herein in their entirety Khandros et al., U.S.Pat. No. 5,148,265, for SEMICONDUCTOR CHIP ASSEMBLIES WITH FAN-IN LEADS,discloses a semiconductor chip having contacts on the periphery of itstop surface is provided with an interposer overlying the central portionof the top surface. Peripheral contact leads extend inwardly from theperipheral contacts to central terminals on the interposer. Theterminals on the interposer may be connected to a substrate usingtechniques commonly employed in surface mounting of electrical devices,such as solder bonding. The leads, and preferably the interposer, areflexible so that the terminals are movable with respect to the contactson the chip, to compensate for differential thermal expansion of thechip and substrate. The terminals on the interposer may be disposed inan area array having terminals disposed at substantially equal spacingsthroughout the area of the interposer, thus providing substantialdistances between the terminals while accommodating all of the terminalsin an area approximately the same size as the area of the chip itself.The interposer may be provided with a compliant layer disposed betweenthe terminals and the chip to permit slight vertical movement of theterminals towards the chip during testing operations. The chip andinterposer assembly may be electrically tested prior to assembly to thesubstrate. A compliant layer disposed between the terminals and the chippermits slight vertical movement of the terminals towards the chipduring testing operations, in which the terminals on the interposer areengaged with an assembly of test probes. The entire assembly is compact.

[0004] Khandros et al., U.S. Pat. No. 5,148,266, for SEMICONDUCTOR CHIPASSEMBLIES HAVING INTERPOSER AND FLEXIBLE LEAD, discloses asemiconductor chip assembly is mounted to contact pads in a compact areaarray. An interposer is disposed between the chip and the substrate. Thecontacts on the chip are connected to terminals on the interposer byflexible leads extending through apertures in the interposer. Theterminals on the interposer in turn are bonded to the contact pads onthe substrate. Flexibility of the leads permits relative movement of thecontacts on the chip relative to the terminals and the contact pads ofthe substrate and hence relieves the stresses caused by differentialthermal expansion. The arrangement provides a compact structure similarto that achieved through flip-chip bonding, but with markedly increasedresistance to thermal cycling damage.

[0005] DiStefano et al., U.S. Pat. No. 5,455,390, for a MICROELECTRONICSUNIT MOUNTING WITH MULTIPLE LEAD BONDING, discloses a component formounting semiconductor chips or other microelectronic units includes aflexible top sheet with an array of terminals on it, and with flexibleleads extending downwardly from the terminals. A compliant dielectricsupport layer surrounds the leads, holding the lead tips in preciselocations. The leads are desirably formed from wire such as gold wire,and have eutectic bonding alloy on their tips. The component can belaminated to a chip or other unit under heat and pressure to form acomplete subassembly with no need for individual bonding to the contactsof the chip. The subassembly can be tested readily and providescompensation for thermal expansion.

[0006] Distefano et al., U.S. Pat. No. 5,518,964, for a MICROELECTRONICMOUNTING WITH MULTIPLE LEAD DEFORMATION AND BONDING, discloses amicroelectronic connection component includes a dielectric sheet havingan area array of elongated, strip-like leads. Each lead has a terminalend fastened to the sheet and a tip end detachable from the sheet. Eachlead extends horizontally parallel to the sheet, from its terminal endto its tip end. The tip ends are attached to a second element, such asanother dielectric sheet or a semiconductor wafer. The first and secondelements are then moved relative to one another to advance the tip endof each lead vertically away from the dielectric sheet and deform theleads into a bent, vertically extensive configuration. The preferredstructures provide semiconductor chip assemblies with a planar areaarray of contacts on the chip, an array of terminals on the sheetpositioned so that each terminal is substantially over the correspondingcontact, and an array of metal S-shaped ribbons connected between theterminals and contacts. A compliant dielectric material may be providedbetween the sheet and chip, substantially surrounding the S-shapedribbons.

[0007] Khandros et al., U.S. Pat. No. 5,679,997, for a SEMICONDUCTORCHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME,discloses semiconductor chip assemblies incorporating flexible,sheet-like elements having terminals thereon overlying the front or rearface of the chip to provide a compact unit. The terminals on thesheet-like element are movable with respect to the chip, so as tocompensate for thermal expansion. A resilient element such as acompliant layer interposed between the chip and terminals permitsindependent movement of the individual terminals toward the chip drivingengagement with a test probe assembly so as to permit reliableengagement despite tolerances.

[0008] Khandros et al., U.S. Pat. No. 5,685,855, for a WAFER-SCALETECHNIQUES FOR FABRICATION OF SEMICONDUCTOR CHIP ASSEMBLIES, discloses amethod wherein semiconductor chip assemblies are fabricated byassembling flexible, sheetlike elements bearing terminals to a wafer,connecting the terminals of each sheetlike element to contacts on thechip, and subsequently severing the chips from the wafer to provideindividual assemblies. Each assembly includes a sheetlike element and achip, arranged so that the terminals on the flexible element are movablewith respect to the chip.

SUMMARY OF THE INVENTION

[0009] Disclosed is a method of ball grid array packaging, comprisingthe steps of providing a semiconductor die having a metal conductorsthereon, covering said metal conductors with an insulative layer,etching through said insulative layer so as to provide one or moreopenings to said metal conductors, depositing a compliant materiallayer, etching through said compliant material layer so as to provideone or more openings to said metal conductors, depositing asubstantially homogenous conductive layer, patterning said conductivelayer so as to bring at least one of said metal conductors in electricalcontact with one or more pads, each said pad comprising a portion ofsaid conductive layer disposed upon said compliant material, andproviding solder balls disposed upon said pads.

[0010] Another aspect of the method further comprises the step ofdepositing a passivation layer prior to said deposition of saidcompliant material layer.

[0011] In another aspect of the method said passivation layer comprisesa silicon nitride layer atop a silicon oxide layer.

[0012] In another aspect of the method said passiviation layer comprisesborosilicate glass.

[0013] In another aspect of the method said metal conductors are ametallic damascene layer.

[0014] In another aspect of the method said metal conductors comprisecopper.

[0015] In another aspect of the method said insulative layer comprises asilicon oxide layer atop a silicon nitride layer.

[0016] In another aspect of the method said step of etching through saidcompliant material is executed in a manner effective in not etching saidinsulative layer and in forming vias of greater width than said openingsthrough said insulative layer.

[0017] In another aspect of the method said conductive layer comprisesaluminum and copper.

[0018] Another aspect of the method further comprising the step ofdepositing a barrier layer prior to said deposition of said conductivelayer.

[0019] In another aspect of the method said barrier layer comprises atleast one of tantalum nitride, titanium nitride, or tungsten nitride.

[0020] In another aspect of the method said compliant material comprisesa poly-imide.

[0021] Disclosed is a ball grid array package, comprising asemiconductor die having a compliant layer thereon and metalliccircuitry therein, a substantially homogenous conductive layer depositedupon said compliant material and patterned so as to bring at least onepoint of said metallic circuitry into electrical contact with one ormore pads, each said pad comprising a portion of said conductive layerdisposed upon said compliant material, and one or more solder ballsdisposed upon said pads.

[0022] In another aspect of the invention said metal circuitry is ametallic damascene layer.

[0023] In another aspect of the invention said metal circuitry comprisescopper.

[0024] In another aspect of the invention said conductive layer isdeposited in-vias, said vias insulated from said metal circuitry by aninsulative layer, said insulative layer having an openings therethroughto permit electrical contact between said metal circuitry and saidconductive layer.

[0025] In another aspect of the invention said conductive layercomprises aluminum and copper.

[0026] Another aspect of the invention further comprises a barrier layerinterposed between said conductive layer and said semiconductor die.

[0027] In another aspect of the invention said barrier layer comprisesat least one of tantalum nitride, titanium nitride, or tungsten nitride.

[0028] In another aspect of the invention said compliant materialcomprises a poly-imide.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 shows the prior art of BGA packaging in cross section.

[0030]FIG. 2 shows an embodiment of the invention in cross-section.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0031] Traditional chip packaging comprises a chip having “legs” aboutits outer periphery that plug into a socket. By using a grid array ofcontacts on the bottom surface of a chip, the number of available leadsis the square of the available leads on the periphery. These are oftenalso referred to as “area array” packaging and comprises a grid array ofpins on the bottom surface of the chip, so called “pin grid arrays”(PGA). By the late 1980's, the pins had been replaced with small solderballs, hence the BGA. This technology is now extended to chip scalepackaging (CSP), wherein the package is built to the scale of the chipitself. This implies the solder balls are directly or nearly directlyattached to the chip, which has a vastly different coefficient oftemperature expansion than the circuit board to which it will beattached, hence the possibility of breaking or shorting connections dueto expansion and contraction is increasing.

[0032] Referring to FIG. 1, these problems are solved with micro-BGAtechnology by interposing a compliant material between the silicon dieand the solder spheres. In this drawing, you see a cross section of thechip, the solder balls 2 on top of the re-routing 3.

[0033] Referring to FIG. 1, we see that the chip 1 is silicon based,having a Cu (dual-) damascene metallization 8 to connect the devices(for simplification reasons only the last Cu metal level is shown, nodevices are shown). The Cu metallization is encapsulated by a siliconnitride layer 9. An oxide layer 13 is used to insulate the aluminum pad6 from the circuitry. Contact holes (vias) are etched into the oxide 13and the silicon nitride 9. An aluminum-copper alloy layer is depositedon top of the oxide 13. Prior to the aluminum copper alloy a barrierlayer 10 is deposited. This barrier layer can either be TaN, TiN or WNor any other metal or metal-nitride or electrically conductive material.After barrier and aluminum-copper alloy deposition the metal layers arepatterned by a lithography and etch step, forming the bond pads. Apassivation layer consisting of silicon oxide 14 and silicon nitride 12is deposited afterwards.

[0034] The aluminum/copper bond pad 6 is brought into electrical contactwith a solder ball 2 by a backend rerouting procedure wherein oxidelayer 13 and nitride layer 12 have been etched through and a reroutingconductor 3, usually made of a copper/gold alloy, has been deposited.The solder balls 2 are then deposited upon the rerouting conductors 3.This allows the solder balls 2 to be in electrical contact with thecircuitry of the chip. The compliant material allows the silicon die toexpand and contract with temperature without affecting the spacing ofthe solder balls 2 and usually comprises a relatively thick polymer,such as a photo-sensitive poly-imide, which is used for patterning thepads.

[0035] The method of the invention is to eliminate the back-endrerouting procedure by modifying the front-end metal deposition. Theprocedure is as follows:

[0036] Referring to FIG. 2, the last Cu layer 8 is covered with asilicon nitride 9 and a silicon oxide 13 layer like in the prior art. Acontact hole (via) is defined by lithography and etched into oxide andnitride to provide electrical contact to the last metal level 6 which isan aluminum copper alloy (AlCu). Afterwards a passivation consisting ofan oxide layer 11 and nitride layer 12 is deposited. Other knownpassivation layers may alternatively be used, such as borosilicate glass(BSG). On top of the passivation a photosensitive poly-imide 4 isdeposited, exposed and developed. A large terminal via is etched intothe nitride 12 and oxide 11 stopping on top of the oxide layer 13. Ithas to be considered, that all of the material deposited into the viaswill be removed to allow the AlCu alloy to contact the Cu (dual-)damascene layer.

[0037] After defining the large contact holes (terminal vias) aconductive layer of preferably aluminum-copper alloy is deposited. Itwill be patterned so that it is part of the circuitry of the device andadditionally provides pads where the solder balls can be placed in theright position for BGA packaging. Hence, the pads are now in directelectrical contact with the circuitry through a single, substantiallyhomogenous, conductive layer. It is preferable to first provide abarrier layer 10 before depositing the conductive layer.

[0038] Traditionally, the solder balls are disposed upon a gold/copperalloy. Because the solder balls in this invention are placed directlyupon a AlCu metallization, one may consider adjusting the soldermaterial to maximally bind to the metal alloy. Generally, so long as thematerial contains copper, there should be little difficulty in bondingto a typical lead/tin alloy solder, so the aluminum/copper alloy shouldbond as satisfactorily as the gold/copper alloy of the prior art.

[0039] As can be seen, the back-end rerouting procedures are completelyeliminated by the invention, thereby saving processing costs and time.Further, reliability is improved because the solder balls are now inimmediate contact with the circuitry of the chip, rather than contactingthrough a conductive intermediary.

[0040] It is to be understood that all physical quantities disclosedherein, unless explicitly indicated otherwise, are not to be construedas exactly equal to the quantity disclosed, but rather as about equal tothe quantity disclosed. Further, the mere absence of a qualifier such as“about” or the like, is not to be construed as an explicit indicationthat any such disclosed physical quantity is an exact quantity,irrespective of whether such qualifiers are used with respect to anyother physical quantities disclosed herein.

[0041] While preferred embodiments have been shown and described,various modifications and substitutions may be made thereto withoutdeparting from the spirit and scope of the invention. Accordingly, it isto be understood that the present invention has been described by way ofillustration only, and such illustrations and embodiments as have beendisclosed herein are not to be construed as limiting to the claims.

What is claimed is:
 1. A method of ball grid array packaging, comprisingthe steps of: providing a semiconductor die having a metal conductorsthereon; covering said metal conductors with an insulative layer;etching through said insulative layer so as to provide one or moreopenings to said metal conductors; depositing a compliant materiallayer; etching through said compliant material layer so as to provideone or more openings to said metal conductors; depositing asubstantially homogenous conductive layer; patterning said conductivelayer so as to bring at least one of said metal conductors in electricalcontact with one or more pads, each said pad comprising a portion ofsaid conductive layer disposed upon said compliant material; andproviding solder balls disposed upon said pads.
 2. The method of claim 1further comprising the step of depositing a passivation layer prior tosaid deposition of said compliant material layer.
 3. The method of claim2 wherein said passivation layer comprises a silicon nitride layer atopa silicon oxide layer.
 4. The method of claim 2 wherein saidpassiviation layer comprises borosilicate glass.
 5. The method of claim1 wherein said metal conductors are a metallic damascene layer.
 6. Themethod of claim 1 wherein said metal conductors comprise copper.
 7. Themethod of claim 1 wherein said insulative layer comprises a siliconoxide layer atop a silicon nitride layer.
 8. The method of claim 1wherein said step of etching through said compliant material is executedin a manner effective in not etching said insulative layer and informing vias of greater width than said openings through said insulativelayer.
 9. The method of claim 1 wherein said conductive layer comprisesaluminum and copper.
 10. The method of claim 1 further comprising thestep of depositing a barrier layer prior to said deposition of saidconductive layer.
 11. The method of claim 10 wherein said barrier layercomprises at least one of tantalum nitride, titanium nitride, ortungsten nitride.
 12. The method of claim 1 wherein said compliantmaterial comprises a poly-imide.
 13. A ball grid array package,comprising a semiconductor die having a compliant layer thereon andmetallic circuitry therein; a substantially homogenous conductive layerdeposited upon said compliant material and patterned so as to bring atleast one point of said metallic circuitry into electrical contact withone or more pads, each said pad comprising a portion of said conductivelayer disposed upon said compliant material; and one or more solderballs disposed upon said pads.
 14. The apparatus of claim 13 whereinsaid metal circuitry is a metallic damascene layer.
 15. The apparatus ofclaim 13 wherein said metal circuitry comprises copper.
 16. Theapparatus of claim 13 wherein said conductive layer is deposited invias, said vias insulated from said metal circuitry by an insulativelayer, said insulative layer having an openings therethrough to permitelectrical contact between said metal circuitry and said conductivelayer.
 17. The apparatus of claim 13 wherein said conductive layercomprises aluminum and copper.
 18. The apparatus of claim 13 furthercomprising a barrier layer interposed between said conductive layer andsaid semiconductor die.
 19. The apparatus of claim 18 wherein saidbarrier layer comprises at least one of tantalum nitride, titaniumnitride, or tungsten nitride.
 20. The apparatus of claim 13 wherein saidcompliant material comprises a poly-imide.